A semiconductor device manufacturing process is divided into a pre-process of forming a plurality of semiconductor circuits on a semiconductor substrate and a post-process of forming semiconductor chips by individually cutting the semiconductor substrate in which a plurality of circuits is formed. In either of the processes, a test for determining the quality of the manufactured semiconductor chip is performed, and the processes are called a pre-process test and a post-process test, respectively. In a test, signals are transmitted and received between a tester and a semiconductor circuit.
In the pre-process test, when semiconductor circuits are tested in the state of the semiconductor substrate, a method of transmitting and receiving signals is broadly divided into a contact method and a noncontact method.
The contact method is a method in which a probe needle is placed against a pad connected to the semiconductor circuit, and the tester and the semiconductor circuit are connected to each other through the probe needle. On the other hand, the noncontact method is a method in which signals are transmitted and received to and from the semiconductor circuit by magnetic coupling or capacitive coupling and the like, and a test is performed through a magnetic coupling probe or a capacitive coupling probe moved closer to the semiconductor circuit. The noncontact method in which a probe needle is not used has an effect of lowering test costs because the probe is not abraded.
In addition, a method of testing a semiconductor circuit includes a function test and a static power source current test.
The function test is a method in which test vectors are input to the semiconductor circuit and an output thereof is compared with an expected value which is previously calculated, to thereby determine the quality of the semiconductor circuit. On the other hand, the static power source current test is a method in which attention is drawn to the fact that a defective semiconductor circuit retains a high static power source current level, and the power source current in the resting state having no fluctuation in the input value is measured and compared with the normal quiescent power source current, to thereby determine the quality of the semiconductor circuit. When the operation of the semiconductor circuit is ensured with a certain width of the power source voltage, the function test and the static power source current test are performed by changing the voltage in the width of the power source voltage. Since the change of the power source voltage or the measurement of the power source current is possible, a high-accuracy test can be performed.
Here, simultaneous testing of a plurality of semiconductor circuit is effective as a method of lowering test costs.
Particularly, as a method of efficiently performing the pre-process test in the state of the semiconductor substrate, Patent Document 1 proposes a method of sharing the power line in a plurality of semiconductor chips. According to this method, it is possible to simultaneously apply the voltage to a plurality of semiconductor chips sharing the power line by placing a needle against a pad of one spot connected to the power line and applying a necessary voltage from the test device.
In addition, Patent Documents 2 and 3 also disclose a structure in which a power source is supplied from one power interconnect to a plurality of semiconductor circuits.
Further, when an overcurrent flows due to a certain defective semiconductor chip, in order to avoid a problem that the test of all semiconductor chips sharing the power line cannot be performed, Patent Document 4 proposes a method in which a fuse is provided in an interconnect between a probing pad leading to the power line connected to a plurality of semiconductor chips and a bonding pad, and the fuse is melted down due to the overcurrent, to thereby electrically decouple a defective semiconductor chip from the common power line.
In addition, as a method of simultaneously performing a quiescent power source current test on a plurality of chips, Patent Document 5 proposes a test method in which a function of cutting off a power source voltage as necessary is given by providing a power source voltage generator and a detector that detecting fluctuation of the power source voltage with the semiconductor chip.
Further, there are Patent Documents 6 to 8 as the background art.    [Patent Document 1] Japanese Unexamined Patent Publication No. H03-34555    [Patent Document 2] Japanese Unexamined Patent Publication No. H06-125063    [Patent Document 3] Japanese Unexamined Patent Publication No. H11-354721    [Patent Document 4] Japanese Unexamined Patent Publication No. 2000-124279    [Patent Document 5] Japanese Unexamined Patent Publication No. 2005-134405    [Patent Document 6] Japanese Unexamined Patent Publication No. 2000-150429    [Patent Document 7] Japanese Unexamined Patent Publication No. 2005-150514    [Patent Document 8] Japanese Unexamined Patent Publication No. H08-148533